1. Field of the Invention
The present invention generally relates to a semiconductor device. More particularly, the present invention relates to a trench-shaped read-only memory having decreased parasitic capacitance. In addition, a method for fabricating the trench-shaped read-only memory is provided.
2. Description of the Related Art
Masked ROMs are nonvolatile memories into which memory states are permanently stored in accordance with custom masks during fabrication. Usually, each memory cell is implemented by a MOS (metal-oxide-semiconductor) transistor. In a masked ROM device, the channel region of a memory cell is selectively implanted with ions to adjust the threshold voltage thereof depending on whether the programmed memory cell is turned on or turned off, to represent a logic "1" or a logic "0" in binary code, respectively.
Referring to FIGS. 1A-1B, the conventional method for fabricating a read-only memory is depicted in cross-sectional views. A semiconductor substrate 1, such as a P-type silicon substrate, is first provided. As shown in FIG. 1A, a pad oxide layer 10 and a silicon nitride layer 11 are subsequently formed over the substrate 1. Then, the silicon nitride layer 11 is patterned and etched by photolithography to define the range of an active region 100 as depicted in FIG. 1A. Afterwards, thermal oxidation of the substrate 1 not covered by the patterned silicon nitride layer 11 forms field oxides 12 as isolating structures. This oxidation step is a so-called LOCOS (local oxidation of silicon) technology. Consequently, the active region 100 is automatically disposed between the field oxides 12.
The silicon nitride layer 11 and the pad oxide layer 10 are thereafter removed to expose the substrate 1. Furthermore, impurities, such as phosphorus-containing or arsenic-containing ions, are implanted into the substrate 1 to form a plurality of N-type bit lines 13 mutually spaced apart in parallel. As is well known in this art, a photoresist layer (not shown in the drawing) with the bit-line pattern should be formed on the substrate 1 prior to the implantation process. Then, thermal oxidation of the surface of the substrate 1 and the bit lines 13 forms dielectric layers 14 and 15, respectively. In particular, the dielectric layers 15 over the bit lines 13 have a thickness greater than the dielectric layers 14 because the doping concentration of the bit lines 13 is heavier than that of the substrate 1 resulting in a higher oxidation rate. Moreover, a polysilicon layer is deposited, as depicted in FIG. 1B, to overlie the field oxides 12 and dielectric layers 14, 15, and is thereafter patterned to form a plurality of word lines 16 spaced apart in parallel. The substrate 1 below each word line 16 and between two adjacent bit lines 13 is the channel region of a memory cell. The bit lines 13 disposed at two ends of the channel region serve as a drain region and a source region, respectively, and the word line 16 thereabove serves as a gate electrode of the memory cell.
Next, as depicted in FIG. 1B, a photoresist layer 110 is formed over the substrate 1 and patterned, in accordance with the customer masks, through photolithography to expose the channel regions to be implanted. After that, by utilizing the photoresist layer 110 as masking, ions 17, such as BF.sub.2.sup.+ or B.sub.11.sup.+, are implanted into the substrate 1 to increase the threshold voltage of the channel regions not covered by the photoresist layer 110 to form a first state region 18. The remainder covered by the photoresist layer 110 is a second state region 19.
Nevertheless, the thickness of the dielectric layer 15 is restricted by oxidation rate as well as the doping concentration of the bit lines 13, which can not effectively decrease the parasitic capacitance between the word lines 16 and the bit lines 13 as well as the substrate 1. In addition, the lateral diffusion that occurs in the bit lines 13 during the formation of the dielectric layers 14 and 15 hinders the application of this structure to high-density read-only memory devices.